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(A) 期刊論文

  1. Lan-Rong Dung, Yen-Lin Lee, and Chun-Ming Wu, 2001, July/October, “A Reconfigurable Architecture for DSP System-on-Chip,” Canadian Journal of Electrical and Computer Engineering, pp.109-113 (SCI) (NSC 89-2215-E-009-119-)
  2. Hsien-Wen Cheng and Lan-Rong Dung, 2004, February, “A Vario-Power Motion Estimation Architecture Using Content-based Subsample Algorithm,” IEEE transactions on Consumer Electronics, pp.349-354 (SCI) (NSC 92-2220-E-009-033-)
  3. Hsien-Wen Cheng and Lan-Rong Dung, 2004, May “EFBLA: a Two-Phase Matching Algorithm for Fast Motion Estimation,” Electronics Letters, Vol.40, pp.660-661 (SCI) (NSC 91-2215-E-009-079-)
  4. T.-H. Chang and L.-R. Dung, 2004, May, “Resonator-based Multi-stage Sigma-Delta Modulator for Wideband Applications with Improved Dynamic Range,” Electronics Letters, Vol.40, pp.652-653 (SCI) (NSC 91-2215-E-009-079-)
  5. Lan-Rong Dung and Meng-Chun Lin, 2004, May, “A Maskable Memory Architecture for Rank-Order Filtering,” IEEE transactions on Consumer Electronics, pp.558-564 (SCI) (NSC 92-2220-E-009-003-)
  6. Teng-Hung Chang and Lan-Rong Dung, 2004, May, “New Wideband Cascaded Sigma-Delta Modulator for Multimode wireless receiver,” IEICE Electronics Express, Vol.1, No.3, pp. 57-62 (SCI) (NSC 91-2215-E-009-079-)
  7. Lan-Rong Dung, 2004, December, “An IP Synthesizer for Limited-Resource DWT Processor,” IEICE transactions on Fundamentals, Vol.E87-A, No.12, pp.3047-3056 (SCI) (NSC 92-2220-E-009-003-)
  8. Lan-Rong Dung and Hsueh-Chih Yang, 2004, December, “On Multiple-Voltage High-Level Synthesis Using Algorithmic Transformations,” IEICE transactions on Fundamentals, Vol.E87-A, No.12, pp.3100-3108 (SCI) (NSC 92-2220-E-009-033-)
  9. Teng-Hung Chang and Lan-Rong Dung, 2005, February, “Dynamic Range Improvement of Multistage Multibit Sigma-Delta Modulator for Low Oversampling Ratios, ” IEICE transactions on Fundamentals, vol.E88-A, no.2, pp.451-460 (SCI) (NSC 93-2220-E-009-023-)
  10. Hsien-Wen Cheng and Lan-Rong Dung, 2005, October, “A Content-based Methodology for Power-Aware Motion Estimation Architecture,” IEEE Transactions on Circuits and Systems II, pp.631-635 (SCI) (NSC 93-2220-E-009-023-)
  11. Meng-Chun Lin, Lan-Rong Dung and Ping-Kuo Weng, 2006, February, “A Ultra-low-power Image Compressor for Capsule Endoscope,” BioMedical Engineering OnLine, Vol.5, pp.14.1-14.8 (SCI) (NSC 94-2220-E-009-023)
  12. Tsung-Hsi Chiang and Lan-Rong Dung, 2006, June, “System Level Verification on High-Level Synthesis of Dataflow Algorithms Using Petri Net,” WSEAS transactions on Circuits and Systems, Issue 6, Vol. 5, pp.790-796 (EI) (NSC 94-2220-E-009-039)
  13. Hsien-Wen Cheng and Lan-Rong Dung, 2006, July, “A Power-Aware Motion Estimation Architecture Using Content-based Subsampling,” Journal of Information Science and Engineering, Vol.22, No.4, pp.799-818 (SCI) (NSC 92-2220-E-009-033-)
  14. Lan-Rong Dung and Hsueh-Chih Yang, 2006, December, “A Parallel-In Folding Technique for High-Order FIR Filter Implementation,” IEICE Transactions on Fundamentals, Vol. E89-A, No.12, pp.3659-3665 (SCI) (NSC 94-2220-E-009-023-)
  15. Chuan-Sheng Lin and Lan-Rong Dung, 2007, February, “A NAND Flash Memory Controller for SD/MMC Flash Memory Card,” IEEE Transactions on Magnetics, Vol.43, No.2, pp.933-935 (SCI)
  16. Tsung-Hsi Chiang and Lan-Rong Dung, 2007, May, “A VLSI Progressive Coding for Wavelet-based Image Compression,” IEEE Transactions on Consumer Electronics, Vol.53, No.2, pp.569-577 (SCI) (NSC 95-2221-E-009-337-MY3)
  17. Tsung-Hsi Chiang and Lan-Rong Dung, 2007, August, “Verification Method of Dataflow Algorithms in High-Level Synthesis,” Journal of Systems and Software, Vol.80, No.8, pp.1256-1270 (SCI) (NSC 94-2220-E-009-039)
  18. Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo, and Kai-Jiun Yang, 2007, November, “A 2.5-V 14-bit, 180-mW Cascaded Sigma-Delta ADC for ADSL2+ Application, ” IEEE Journal of Solid State Circuits, Vol.42, No.11, pp.2357-2368 (SCI) (NSC 95-2221-E-009-337-MY3)
  19. Meng-Chun Lin and Lan-Rong Dung, 2008, February, “On VLSI Design of Rank-Order Filtering using DCRAM Architecture,” Integration, the VLSI Journal, Vol.41, pp.193-209 (SCI) (NSC 95-2221-E-009-337-MY3)
  20. Teng-Hung Chang and Lan-Rong Dung, 2008, July, “Fourth-Order Cascade Sigma-Delta Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications,” IEEE Transactions on Circuits and Systems I, Vol.55, No.6, pp.1722-1732 (SCI)(NSC 95-2221-E-009-337-MY3)
  21. Tsung-Hsi Chiang and Lan-Rong Dung, 2008, April, “Verification Method on Dataflow Scheduling,” International Journal of Software Engineering and Knowledge Engineering, Vol.18, No.6, pp.737-758 (SCI) (NSC 94-2220-E-009-039)
  22. Lan-Rong Dung and Meng-Chun Lin, 2008, December, “Wide-Range Motion Estimation Architecture with Dual Search Windows for High Resolution Video Coding,” IEICE Transactions on Fundamentals, Vol. E91-A, No.12, pp.3638-3650 (SCI) (NSC 95-2221-E-009-337-MY3).
  23. Lan-Rong Dung and Zhi-Wei Huang, 2009, June, “A K-Best Sphere Decoder Using Multistage Structure,” International Journal of Electrical Engineering, Vol.16, No.3, pp.231-239 (SCI)(NSC 94-2220-E-009-033-)
  24. Meng-Chun Lin and Lan-Rong Dung, 2010, September, “A Content-Motion-Aware Motion Estimation for Quality-Stationary Video Coding,” EURASIP Journal on Advances in Signal Processing, Vol. 2010, Article ID 403634, 12 pages (SCI)(NSC 98-2221-E-009-138-)
  25. Lan-Rong Dung and Yin-Yi Wu, 2010, December, "A Wireless Narrow-Band Imaging Chip for Capsule Endoscope," IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 6, pp. 462-468 (SCI)(NSC 98-2221-E-009-138-)
  26. Meng-Chun Lin and Lan-Rong Dung, 2011, March, “A Subsample-based Low-Power Image Compressor for Capsule Gastrointestinal Endoscopy,” EURASIP Journal on Advances in Signal Processing, Vol. 2011, Article ID 257095, 12 pages (SCI)(NSC 98-2221-E-009-138-)

(B) 研討會論文

  1. Lan-Rong Dung, Yen-Lin Lee, and Chun-Ming Wu, 2001, July, “A Reconfigurable Architecture for DSP System-on-a-Chip,” SCI2001 (NSC 89-2215-E-009-119-)
  2. Lan-Rong Dung, Yen-Lin Lee, and Chun-Ming Wu, 2001, September, “A Reconfigurable Architecture for DSP SOC,” IWMATT2001 (NSC 89-2215-E-009-119-)
  3. Yen-Lin Lee and Lan-Rong Dung, 2001, August, “The Configurable Scheduler for IP-based SOC Synthesis,” the 12th VLSI Design/CAD Symposium (NSC 89-2215-E-009-119-)
  4. Ting-Hsun Wei, Shiuh-Rong Huang, and Lan-Rong Dung, 2002, “An Automated IP Synthesizer for Limited-Resource DWT Processors,” ICASSP 2002 (NSC 90-2215-E-009-083-)
  5. Shiuh-Rong Huang and Lan-Rong Dung, 2002, “VLSI Implementation for MAC-Level DWT Architecture,” ISVLSI 2002 (NSC 90-2215-E-009-083-)
  6. Shiuh-Rong Huang and Lan-Rong Dung, 2002, “A MAC-Level Synthesis of Resource-Constrained DWT SIP,” the 13th VLSI Design/CAD Symposium (NSC 90-2215-E-009-083-)
  7. Hsien-Wen Cheng and Lan-Rong Dung, 2002, “EFBLA: A Two-phase matching algorithm for FAST motion estimation,” PCM 2002 (NSC 91-2215-E-009-079-)
  8. Hsien-Wen Cheng and Lan-Rong Dung, 2003, “A Power-Aware Architecture for Motion Estimation,” the 14th VLSI Design/CAD Symposium (NSC 91-2215-E-009-079-)
  9. T.-H. Chang and L.-R. Dung, 2003, “On the Design of Low-Voltage, Low-Power Analog Adder and Multiplier Based on Floating Gate Technique,” the 14th VLSI Design/CAD Symposium (NSC 91-2215-E-009-079-)
  10. Hsien-Wen Cheng and Lan-Rong Dung, 2003, “A Novel Vario-Power Architecture of Motion Estimation Using a Content-based Subsample Algorithm,” SiPS 2003 (NSC 92-2220-E-009-003-)
  11. Hsien-Wen Cheng, Lan-Rong Dung, Jien-Hwang Yen, and Jiann-Jau Wang, 2003, “A content-based motion estimation algorithm for power-aware architecture,” ISPA 2003 (NSC 92-2220-E-009-033-)
  12. Hsien-Wen Cheng and Lan-Rong Dung, 2004, “A Power-Aware ME Architecture Using Subsample Algorithm,” ISCAS 2004 (NSC 92-2220-E-009-003-)
  13. Meng-Chun Lin and Lan-Rong Dung, 2004, “A Maskable Memory Based Rank-Order Filter Design,” the 15th VLSI Design/CAD Symposium (NSC 92-2220-E-009-003-)
  14. Jieh-Hwang Yen, Chi-Yuan Shen, Hsueh-Chih Yang and Lan-Rong Dung, 2004, “Power Awareness Estimation on Truncated Multiplier Design,” the 15th VLSI Design/CAD Symposium (NSC 92-2220-E-009-033-)
  15. Hsueh-Chih Yang, Chih-Kai Chang, Jieh-Hwang Yen and Lan-Rong Dung, 2004, “On Multiple-Voltage High-Level Synthesis Using Algorithmic Transformations,” the 15th VLSI Design/CAD Symposium (NSC 92-2220-E-009-003-)
  16. Meng-Chun Lin and Lan-Rong Dung, 2004, December, “A maskable memory architecture for rank-order filtering,” APCCAS 2004
  17. Hsueh-Chih Yang and Lan-Rong Dung, 2005, January, “On multiple-voltage high-level synthesis using algorithmic transformations,” ASP-DAC 2005 (NSC 93-2220-E-009-023-)
  18. Teng-Hung Chang and Lan-Rong Dung, 2005, April, “On Improving Dynamic Range of Wideband Multistage Sigma-Delta Modulator Using Nonlinear Oscillation,” VLSI-DAT 2005
  19. Tsung-Hsi Chiang, Lan-Rong Dung and Ming-Feng Yaung, 2005, May “Modeling and Formal Verification of Dataflow Graph in System-Level Design Using Petri net,” ISCAS 2005 (NSC 93-2220-E-009-023-)
  20. Teng-Hung Chang, Lan-Rong Dung and Jwin-Yen Guo, 2005, May, “On Reducing Leakage Quantization Noise of Multistage Sigma-Delta Modulator Using Nonlinear Oscillation,” ISCAS 2005
  21. Jieh-Hwang Yen, Lan-Rong Dung and Chi-Yuan Shen, 2005, May, “Design of Power-Aware Multiplier with Graceful Quality-Power Trade-Offs,” ISCAS 2005 (NSC 93-2220-E-009-023-)
  22. Tsung-Hsi Chiang and Lan-Rong Dung, 2005, August, “System-Level Verification of Dataflow Graph Using Petri net model,” the 16th VLSI Design/CAD Symposium
  23. Shu-Der Lan, Jieh-Hwang Yen and Lan-Rong Dung, 2005, August, “On Low-Power Turbo Decoder Design using Early Give-Up and Reuse Techniques,” the 16th VLSI Design/CAD Symposium
  24. Hsueh-Chih Yang and Lan-Rong Dung, 2005, August, “Cost-Efficient Folding Techniques for Long-Length FIR Filter Implementation,” the 16th VLSI Design/CAD Symposium
  25. Lan-Rong Dung, Meng-Chun Lin, Tai-You Chen, Yue-Zhang Song, and Ping-Kuo Weng, 2005, August, “Implementation of Ultra-Low-Power Image Compressor for Capsule Endoscope,” the 16th VLSI Design/CAD Symposium
  26. Tsung-Hsi Chiang and Lan-Rong Dung, 2006, May “System-Level Verification on High-Level Synthesis of Dataflow Graph,” ISCAS 2006
  27. Meng-Chun Lin, Lan-Rong Dung, Chih-Wei Huang, Jun-Way Lyu, and Hsin-Cheng Lai, 2006, August, “A Subsample-based Motion Estimation for Quality-Stationary Video Coding,” the 17th VLSI Design/CAD Symposium
  28. Tsung-hsi Chiang, Lan-Rong Dung, and Shih-Jay Huang, 2006, August, “A Memory-Saving VLSI Implementation of Progressive Image Coding,” the 17th VLSI Design/CAD Symposium
  29. Meng-Chun Lin and Lan-Rong Dung, 2006, October, ”An Improved Ultra-Low-Power Subsample-based Image Compressor for Capsule Endoscope,” MIST 2006
  30. Chuan-Sheng Lin, Kuang-Yuan Chen, and Lan-Rong Dung, 2006, August, ”A NAND Flash Memory Controller for SD/MMC Flash Memory Card,” APDSC 2006
  31. Meng-Chun Lin, Lan-Rong Dung, and Hsuan-Po Lin, 2006, December, “A Subsample-based Motion Estimation for Quality-Stationary Video Coding,” APCCAS 2006
  32. Chuan-Sheng Lin, Kuang-Yuan Chen, Yu-Hsian Wang, and Lan-Rong Dung, 2006, December, ”A NAND Flash Memory Controller for SD/MMC Flash Memory Card,” ICECS 2006
  33. Teng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo, and Kai-Jiun Yang, 2006, November, “A 2.5-V 14-bit 180-mW Cascaded Sigma-Delta ADC for ADSL2+ Applications,” A-SSCC 2006
  34. Meng-Chun Lin, Lan-Rong Dung, and Ping-Kuo Weng, 2006, Nonember, “A Cardinal Image Compression for Capsule Endoscope,” BioCAS 2006
  35. Tsung-Hsi Chiang and Lan-Rong Dung, 2006, December, “High-Quality Image Compression for Gastrointestinal Endoscope,” BMES 2006
  36. Hsueh-Chih Yang and Lan-Rong Dung, 2007, June, “An Accurate Lithium-Ion Battery Gas Gauge Using Two-Phase STC Modeling,” ISIE 2007
  37. Lan-Rong Dung and Tsung-Hsi Chiang, 2007, July, “On System-Level Verification for VLSI Signal Processing,” SPECTS 2007
  38. Lan-Rong Dung and Tsung-His Chiang, 2007, November, “High-Quality Image Compression for Gastrointestinal Endoscope,” BioCAS 2007
  39. Lan-Rong Dung, Zhi-Wei Huang, Chang-Hsiang Lien, and Jhih-Hen Ciu,”A K-Best Sphere Decoder Using Multistage Structure,” VLSI/CAD 2008
  40. Lan-Rong Dung, Jyun-Che Ho, Chih-Sheng Chen, and Chia-Hung Chen,”Analysis on Loop-Delay Compensation Continuous-Time Sigma-Delta ADC,” VLSI/CAD 2008
  41. Meng-Chun Lin, Lan-Rong Dung, and Jhih-Hen Ciu, “Motion Estimation with Dual Search Windows for High Resolution Video Coding,” VLSI/CAD 2008
  42. Lan-Rong Dung, Yin-Yi Wu, Hsin-Cheng Lai, and Ping-Kuo Weng, 2008, November, “A Modified H.264 Intra-frame Video Encoder for Capsule Endoscope,” BioCAS 2008.
  43. Meng-Chun Lin and Lan-Rong Dung, 2008, December, “Two-Step Windowing Technique for Wide Range Motion Estimation,” APCCAS 2008
  44. Lan-Rong Dung, Yung-Lin Chuang, Hung-Cheng Wan, and Hsiang-Fu Yuan, 2009, August, “Fast Calibration Techniques for Auto-Stitich of Camera Array Image,” VLSI/CAD 2009
  45. Lan-Rong Dung, Yin-Yi Wu, Zen-Han Chang, and Hung-Cheng Wan, 2009, August, “A Hybrid Iterative Demosaicking Method Using the Inter-plane Frequency Correlation for Bayer CFA,” VLSI/CAD 2009
  46. Lan-Rong Dung, Yin-Yi Wu, and Ping-Kuo Weng, 2009, December, “A Wireless Narrow-Band Imaging Chip for Capsule Endoscope,” BioCAS 2009
  47. Lan-Rong Dung and Jieh-Hwang Yen, 2010, July, “ILP-Based Algorithm for Lithium-Ion Battery Charging Profile,” ISIE 2010
  48. Lan-Ron Dung, Jieh-An Chen, Chieh-Tsen Lin, and Jieh-Hwang Yen, 2010, August, “An ILP-Based Algorithm for Lithium-Ion Battery Charging Profile,” VLSI/CAD 2010
  49. Lan-Rong Dung, Chang-Hsiang Lien, Yao-Ming Yang, and Guan-Ying Lai, 2010, August, “Constructing Low-Density Parity-Check Code by Priority Based Cycle Elimination Algorithm,” VLSI/CAD 2010
  50. Jieh-Hwang Yen, Po-Cheng Fan, Lan-Rong Dung, and Fa-Hwa Shieh, 2011, April, "The Prototype Implementation of a Varying Current Charger for Aged Rechargeable Lithium-Ion Batteries," IEME 2011
  51. Lan-Rong Dung, Tang-Hsuan Hong, Chang-Min Huang, and Yin-Yi Wu, “ A Detachable Endoscope Based on Capsule Endoscope for GI Examination,” CET 2011
  52. Ren-Yu Huang, Lan-Rong Dung, and Yin-Yi Wu, “An Image Stitching Algorithm based on Inward Image Sensing,” CET 2011

(C) 專書及專書論文

  1. 董蘭榮, 2001, Xilinx FPGA 電路設計與實習,滄海書局
  2. 王駿發,李昆忠, 謝明得, 李聰, 王朝欣, 董蘭榮, 黃穎聰, 系統單晶片概論 SOC-SYSTEM ON CHIPS, McGraw-Hill, 2006

(D) 技術報告及其他

  1. Lan-Rong Dung, 2001, March, “The Study on System-on-Chip Integration Technology for Digital Audio Systems,” Lee and MTI Center Workshop, 2001
  2. 董蘭榮, 2001, November, 對以智財單元為基系統晶片設計之驗證與測試技術開發研究--- 子計畫一:與組織探索階段互動之系統階層驗證技術, 九十年度國科會微電子學門成果發表研討會 (NSC 89-2215-E-009-119-)
  3. Lan-Rong Dung, 2002, March, “The Study on System-on-Chip Integration Technology for Digital Audio Systems,” Lee and MTI Center Workshop, 2002
  4. 董蘭榮, 2002, November, 對以智財單元為基系統晶片設計之驗證與測試技術開發研究--- 子計畫一:與組織探索階段互動之系統階層驗證技術, 九十一年度國科會微電子學門成果發表研討會 (NSC 90-2215-E-009-083-)
  5. 董蘭榮, 2003, November, 對以智財單元為基系統晶片設計之驗證與測試技術開發研究--- 子計畫一:與組織探索階段互動之系統階層驗證技術, 九十二年度國科會微電子學門成果發表研討會 (NSC 91-2215-E-009-079-)
  6. 董蘭榮, 2004, August, 對以智財單元為基系統晶片設計之驗證測試診斷技術開發研究--- 子計畫一:系統晶片之軟硬體共驗證技術, 九十三年度國科會微電子學門成果發表研討會 (NSC 92-2220-E-009-003-)
  7. 董蘭榮, 2004, November, 先進電子設計自動化技術研發---子計畫六:用於奈米晶片系統設計之功率意識高階合成研究(1/3), 九十三年度國科會微電子學門成果發表研討會 (NSC 92-2220-E-009-033-)
  8. 董蘭榮, 2005, August, 先進電子設計自動化技術研發---子計畫六:用於奈米晶片系統設計之功率意識高階合成研究(2/3), 九十四年度國科會微電子學門成果發表研討會 (NSC 93-2220-E-009-023-)
  9. 張騰轟,董蘭榮, 2006,“寬頻多級多位元積分三角調變器,”中華民國專利發明第I254511號
  10. 巫穎毅, 翁炳國, 董蘭榮, 林盟淳, 廖文彬, 戴禮國, 2010, "影像壓縮裝置及其方法," 中華民國專利發明第I330499號
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